1. Field of the Invention
The present invention relates to a method of accurately measuring the distribution of an interface state density generated in a semiconductor device having a metal-insulator-semiconductor (MIS) structure.
2. Description of the Background Art
Characteristics of a semiconductor device having a MIS structure are largely changed by the presence of an interface state in the device. For determination of the characteristics of the semiconductor device, it is necessary to measure the distribution of an interface state density in the MIS structure of the semiconductor device. Some methods of measuring the interface state have been proposed, e.g., in Document 1 (C. N. Berglund, IEEE Trans. Electron Devices, ED-13, 701-705 (1966)) and in Document 2 (M. Kuhn, Solid-State Electronics, 13, 873-885 (1970)). In these methods, quasi-static C-V characteristics are initially measured. The solid curve of FIG. 4 shows an example of a quasi-static C-V curve indicative of the quasi-static C-V characteristics.
A surface potential is calculated from the quasi-static C-V characteristics (indicated by the solid curve of FIG. 4). C-V characteristics of an ideal MIS structure (hereinafter referred to as "ideal C-V characteristics") in which the interface state is absent, are determined on the basis of the conventionally known arithmetic expression. The dotted curve of FIG. 4 is an ideal C-V curve indicative of the ideal C-V characteristics. Comparison is made between the quasi-static C-V curve (or the solid curve of FIG. 4) and the ideal C-V curve (or the dotted curve of FIG. 4) to determine the interface state density distribution in the MIS structure.
As disclosed in Document 2, the surface potential .phi..sub.S (V.sub.G) of the MIS structure when a gate voltage V.sub.G is applied to the metal serving as a gate electrode is derived from the following expression: ##EQU1## where V.sub.ACC is the gate voltage when majority carriers are accumulated in the semiconductor; C.sub.QS (V.sub.G) is the measured capacitance of the MIS structure when the gate voltage V.sub.G is applied; C.sub.O is the capacitance of a gate insulative film or an insulator capacitance; and .DELTA. is the additive constant. As is known from (1), the expression for deriving the surface potential .phi..sub.S (V.sub.G) includes the additive constant .DELTA.. The flat band voltage V.sub.FB ' of the ideal C-V curve (or the dotted curve of FIG. 4) sometimes is the value of .DELTA.' from the flat band voltage V.sub.FB of the quasi-static C-V curve (or the solid curve of FIG. 4). As a result, there has been a problem that the interface state density distribution in the MIS structure cannot be determined accurately.
The interface state density distribution determined in this manner has another problem. FIG. 5 shows an example of the interface state density distribution determined by the above-mentioned method. E.sub.V represents energy level at the upper edge of a valence band, and E.sub.C represents energy level at the lower edge of a conduction band.
An interface trap in the MIS structure becomes an acceptor type in an energy region above a mid-gap E.sub.MG in FIG. 5, and becomes a donor type in an energy region below the mid-gap E.sub.MG. Thus, the polarity of the interface trap is inverted within a band gap of the semiconductor. As shown in FIG. 5, the interface state density is negative in a region below an energy E.sub.FB (=q.multidot.V.sub.FB). In this region, the logarithm of the interface state density cannot be calculated. Accordingly, changes in the logarithm of the interface state density in relation to the energy level between the energy levels E.sub.V and E.sub.C cannot be found.